tm november 2009 fdp10n50u / FDPF10N50UT n-channel mosfet ?2008 fairchild semiconductor corporation fdp10n50u / FDPF10N50UT rev. a -1 www.fairchi ldsemi.com 1 unifet tm fdp10n50u / FDPF10N50UT n-channel mosfet 500v, 8a, 1.05 ? features ?r ds(on) = 0.85 ? ( typ.) @ v gs = 10v, i d = 4a ? low gate charge ( typ. 18nc) ? low c rss ( typ. 9pf) ? fast switching ? 100% avalanche tested ? improved dv/dt capability ? rohs compliant description these n-channel enhancement mode power field effect transis- tors are p roduced using fa irchilds proprietary, planar stripe, dmos technology. this advan ce technology has been especially tailored to mini- mize on-state r esistance, prov ide sup erior switching per for- mance, and wit hstand high ener gy pulse in th e avalanche an d commutation mode. t hese devices are w ell su ited fo r high ef fi- cient switching mode power supplies and active power factor correction. d g s to-220f fdpf series g s d to-220 fdp series g d s mosfet maximum ratings t c = 25 o c unless otherwise noted* thermal characteristics symbol parameter fdp10n50u FDPF10N50UT units v dss drain to source voltage 500 v v gss gate to source voltage 30 v i d drain current -continuous (t c = 25 o c) 8 8* a -continuous (t c = 100 o c) 4.8 4.8* i dm drain current - pulsed (note 1) 32 32* a e as single pulsed avalanche energy (note 2) 320 mj i ar avalanche current (note 1) 8 a e ar repetitive avalanche energy (note 1) 12.5 mj dv/dt peak diode recovery dv/dt (note 3) 20 v/ns p d power dissipation (t c = 25 o c) 125 42 w - derate above 25 o c1 . 0 0 . 3 3 w / o c t j , t stg operating and storage temperature range -55 to +150 o c t l maximum lead temperature for soldering purpose, 1/8 from case for 5 seconds 300 o c symbol parameter fdp10n50u FDPF10N50UT units r ? jc thermal resistance, junction to case 1.0 3.0 o c/w r ? ja thermal resistance, junction to ambient 62.5 62.5 *drain current limited by maximum junction temperature
fdp10n50u / FDPF10N50UT n-channel mosfet fdp10n50u / FDPF10N50UT rev. a-1 www.fairchi ldsemi.com 2 package marking and ordering information t c = 25 o c unless otherwise noted electrical characteristics off characteristics on characteristics dynamic characteristics switching characteristics drain-source diod e characteristics device marking device package reel size tape width quantity fdp10n50u fdp10n50u to-220 - - 50 FDPF10N50UT FDPF10N50UT to-220f - - 50 symbol parameter test conditions min. typ. max. units bv dss drain to source breakdown voltage i d = 250 ? a, v gs = 0v, t j = 25 o c 500 - - v ? bv dss ? t j breakdown voltage temperature coefficient i d = 250 ? a, referenced to 25 o c-0.6-v/ o c i dss zero gate voltage drain current v ds = 500v, v gs = 0v - - 25 ? a v ds = 400v, t c = 125 o c - - 250 i gss gate to body leakage current v gs = 30v, v ds = 0v - - ? 100 na v gs(th) gate threshold voltage v gs = v ds , i d = 250 ? a3 . 0-5 . 0v r ds(on) static drain to source on resistance v gs = 10v, i d = 4a - ? 0.85 1.05 ? g fs forward transconductance v ds = 20v, i d = 4a (note 4) -8.5-s c iss input capacitance v ds = 25v, v gs = 0v f = 1mhz - 850 1130 pf c oss output capacitance - 115 155 pf c rss reverse transfer capacitance - 9 13.5 pf q g total gate charge at 10v v ds = 400v, i d = 10a v gs = 10v (note 4, 5) -1824nc q gs gate to source gate charge - 5 - nc q gd gate to drain miller charge - 7.5 - nc t d(on) turn-on delay time v dd = 250v, i d = 10a r g = 25 ??? v gs = 10v (note 4, 5) -1540ns t r turn-on rise time - 38 86 ns t d(off) turn-off delay time - 46 102 ns t f turn-off fall time - 33 76 ns i s maximum continuous drain to source diode forward current - - 8 a i sm maximum pulsed drain to source diode forward current - - 32 a v sd drain to source diode forward voltage v gs = 0v, i sd = 8a - - 1.6 v t rr reverse recovery time v gs = 0v, i sd = 8a di f /dt = 100a/ ? s (note 4) -44-ns q rr reverse recovery charge - 45 - nc notes: 1: repetitive rating: pulse width limi ted by maximum junction temperature 2: l = 10mh, i as = 8a, v dd = 50v, r g = 25 ? , starting t j = 25c 3: i sd ?? 8a, di/dt ?? 200a/ ? s, v dd ?? bv dss , starting t j = 25c 4: pulse test: pulse width ?? 300 ? s, duty cycle ?? 2% 5: essentially independent of operating temperature typical characteristics
fdp10n50u / FDPF10N50UT n-channel mosfet fdp10n50u / FDPF10N50UT rev. a-1 www.fairchi ldsemi.com 3 typical performance characteristics figure 1. on-region characteristics figure 2. transfer characteristics figure 3. on-resistance variation vs. figure 4. body diode forward voltage drain current and gate vo ltage variation vs. source current and temperature figure 5. capacitance characteristics figure 6. gate charge characteristics 0.1 1 10 20 1 10 20 v gs = 15.0 v 10.0 v 8.0 v 7.0 v 6.5 v 6.0 v 5.5 v *notes: 1. 250 ? s pulse test 2. t c = 25 o c i d ,drain current[a] v ds ,drain-source voltage[v] 2468 0.1 1 10 20 25 o c 150 o c *notes: 1. v ds = 20v 2. 250 ? s pulse test v gs ,gate-source voltage[v] i d ,drain current[a] 0 5 10 15 20 0.8 1.0 1.2 1.4 1.6 *note: t c = 25 o c v gs = 20v v gs = 10v r ds(on) [ m ? ] , drain-source on-resistance i d , drain current [a] 0.00.51.01.52.0 1 10 30 *notes: 1. v gs = 0v 2. 250 ? s pulse test 150 o c i s , reverse drain current [a] v sd , body diode forward voltage [v] 25 o c 0 5 10 15 20 0 2 4 6 8 10 *note: i d = 8a v ds = 100v v ds = 250v v ds = 400v v gs , gate-source voltage [v] q g , total gate charge [nc] 0.1 1 10 30 0 500 1000 1500 2000 c oss c iss c iss = c gs + c gd ( c ds = shorted ) c oss = c ds + c gd c rss = c gd *note: 1. v gs = 0v 2. f = 1mhz c rss capacitances [pf] v ds , drain-source voltage [v]
fdp10n50u / FDPF10N50UT n-channel mosfet fdp10n50u / FDPF10N50UT rev. a-1 www.fairchi ldsemi.com 4 typical performance characteristics (continued) figure 7. breakdown voltage variation figure 8. maximum safe operating area vs. temperature - FDPF10N50UT figure 9. maximum drain current vs. case temperature figure 10. transient thermal response curve - FDPF10N50UT -100 -50 0 50 100 150 200 0.88 0.92 0.96 1.00 1.04 1.08 1.12 1.16 *notes: 1. v gs = 0v 2. i d = 250 ? a bv dss , [normalized] drain-source breakdown voltage t j , junction temperature [ o c ] 1 10 100 1000 0.01 0.1 1 10 50 10 ? s 100 ? s 1ms 10ms i d , drain current [a] v ds , drain-source voltage [v] operation in this area is limited by r ds(on) *notes: 1. t c = 25 o c 2. t j = 150 o c 3. single pulse dc 25 50 75 100 125 150 0 2 4 6 8 10 i d , drain current [a] t c , case temperature [ o c ] 10 -5 10 -4 10 -3 10 -2 10 -1 11010 2 0.005 0.01 0.1 1 5 0.01 0.1 0.2 0.05 0.02 *notes: 1. z ? jc (t) = 3.0 o c/w max. 2. duty factor, d= t 1 /t 2 3. t jm - t c = p dm * z ? jc (t) 0.5 single pulse thermal response [ z ? jc ] rectangular pulse duration [sec] t 1 p dm t 2
fdp10n50u / FDPF10N50UT n-channel mosfet fdp10n50u / FDPF10N50UT rev. a-1 www.fairchi ldsemi.com 5 gate charge test circuit & waveform resistive switching test circuit & waveforms unclamped inductive switching test circuit & waveforms
fdp10n50u / FDPF10N50UT n-channel mosfet fdp10n50u / FDPF10N50UT rev. a-1 www.fairchi ldsemi.com 6 peak diode recovery dv/dt test circuit & waveforms dut v ds + _ driver r g sam e type as du t v gs ? dv/dt controlled by r g ?i sd controlled by pulse period v dd l i sd 10v v gs ( d r iv e r ) i sd ( d u t ) v ds ( dut ) v dd body diode forw ard voltage drop v sd i fm , body diode forw ard current b ody diode reverse c urrent i rm b ody diode recovery dv/dt di/dt d = gate pulse w idth g ate pulse period -------------------------- dut v ds + _ driver r g sam e type as du t v gs ? dv/dt controlled by r g ?i sd controlled by pulse period v dd l l i sd 10v v gs ( d r iv e r ) i sd ( d u t ) v ds ( dut ) v dd body diode forw ard voltage drop v sd i fm , body diode forw ard current b ody diode reverse c urrent i rm b ody diode recovery dv/dt di/dt d = gate pulse w idth g ate pulse period -------------------------- d = gate pulse w idth g ate pulse period --------------------------
fdp10n50u / FDPF10N50UT n-channel mosfet fdp10n50u / FDPF10N50UT rev. a-1 www.fairchi ldsemi.com 7 mechanical dimensions to-220
fdp10n50u / FDPF10N50UT n-channel mosfet fdp10n50u / FDPF10N50UT rev. a-1 www.fairchi ldsemi.com 8 package dimensions dimensions in millimeters to-220f potted * front/back side isolation voltage : 2500v
fdp10n50u / FDPF10N50UT n-channel mosfet fdp10n50u / FDPF10N50UT rev. a-1 www.fa irchildsemi.com 9 trademarks the following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes wi thout further notice to any products herein to improve reliability, fu nction, o r desi gn. fairchild does n ot assume any liability ar ising ou t o f the appl ication or u se of any product or circuit described herein; neither does it convey an y license under its patent rights , nor the rights of others. these specifications do not expand t he terms of fairchilds worldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchilds products are not authorized for use as critical co mponents in life support de vices or systems without the express written approval of fai rchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use pr ovided in t he labe ling, can be reasonably expected to result in a significant injury of the user. 2. a cr itical compon ent in an y component of a lif e supp ort, d evice, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms accupower? 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